sv_port_sim

0.1.0

SvPortSim: Elixir interface for driving Verilated SystemVerilog modules through Ports, with each simulation instance managed as a GenServer.

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2 Dependencies

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Dependencies of sv_port_sim

2 dependencies

Package	Requirement
docker_availability	~> 1.0
nstandard	~> 0.3

mix.exs

rebar.config

Gleam

erlang.mk

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Jun 07, 2026

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Apache-2.0

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