sv_port_sim
0.1.0
SvPortSim: Elixir interface for driving Verilated SystemVerilog modules through Ports, with each simulation instance managed as a GenServer.
Current section
1 Version
Jump to
Current section
1 Version
Checksum
Dependency Config
mix.exs
rebar.config
Gleam
erlang.mk
Package Details
this version
13
yesterday
13
last 7 days
13
all time
13