sv_port_sim

0.2.0

SvPortSim: Elixir interface for driving Verilated SystemVerilog modules through Ports, with each simulation instance managed as a GenServer.

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June 09, 2026

June 07, 2026

Version	Publish Date	Note	Actions
0.2.0	June 09, 2026
0.1.0	June 07, 2026

2 versions of 2 total

mix.exs

rebar.config

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erlang.mk

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Apache-2.0

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