sv_port_sim

0.2.0

SvPortSim: Elixir interface for driving Verilated SystemVerilog modules through Ports, with each simulation instance managed as a GenServer.

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Jun 09, 2026	Publish documentation for release 0.2.0
Jun 09, 2026	Publish release 0.2.0
Jun 07, 2026	Publish documentation for release 0.1.0
Jun 07, 2026	Publish release 0.1.0

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mix.exs

rebar.config

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Apache-2.0

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