Packages
nerves_system_br
1.23.1
1.34.0
1.33.9
1.33.8
1.33.7
1.33.6
1.33.5
1.33.4
1.33.3
1.33.2
1.33.1
1.33.0
1.32.5
1.32.4
1.32.3
1.32.2
1.32.1
1.32.0
1.31.7
1.31.6
1.31.5
1.31.4
1.31.3
1.31.2
1.31.1
1.31.0
1.30.1
1.30.0
1.29.3
1.29.2
1.29.1
1.29.0
1.28.3
1.28.2
1.28.1
1.28.0
1.27.3
1.27.2
1.27.1
1.27.0
1.26.1
1.26.0
1.25.3
1.25.2
1.25.1
1.25.0
1.24.1
1.24.0
1.23.3
1.23.2
1.23.1
1.23.0
1.22.8
1.22.7
1.22.6
1.22.5
1.22.4
1.22.3
1.22.2
1.22.1
1.22.0
1.21.6
1.21.5
1.21.4
1.21.3
1.21.2
1.21.1
1.21.0
1.20.6
1.20.5
1.20.4
1.20.3
1.20.2
1.20.1
1.20.0
1.19.1
1.19.0
1.18.6
1.18.5
1.18.4
1.18.3
1.18.2
1.18.1
1.18.0
1.17.4
1.17.3
1.17.2
1.17.1
1.17.0
1.16.5
1.16.4
1.16.3
1.16.2
1.16.1
1.16.0
1.15.2
1.15.1
1.15.0
1.14.5
1.14.4
1.14.3
1.14.2
1.14.1
1.14.0
1.13.8
1.13.7
1.13.6
1.13.5
1.13.4
1.13.3
1.13.2
1.13.1
1.13.0
1.12.4
1.12.3
1.12.2
1.12.1
1.12.0
1.12.0-rc.0
1.11.4
1.11.3
1.11.2
1.11.1
1.11.0
1.10.3
1.10.2
1.10.1
1.10.0
1.9.5
1.9.4
1.9.3
1.9.2
1.9.1
1.9.0
1.8.6
1.8.5
1.8.4
1.8.3
1.8.2
1.8.1
1.8.0
1.7.3
1.7.2
1.7.1
1.7.0
1.6.8
1.6.7
1.6.6
1.6.5
1.6.4
1.6.3
1.6.2
1.6.1
1.6.0
1.5.6
1.5.5
1.5.4
1.5.3
1.5.2
1.5.1
1.5.0
1.4.5
1.4.4
1.4.3
1.4.2
1.4.1
1.4.0
1.3.2
1.3.1
1.3.0
1.2.2
1.2.1
1.2.0
1.1.0
1.0.1
1.0.0
1.0.0-rc.4
1.0.0-rc.3
1.0.0-rc.2
1.0.0-rc.1
1.0.0-rc.0
0.17.0
0.16.4
0.16.3
0.16.2
0.16.1-2017-11
0.16.0-2017-11
0.15.1
0.15.0
0.14.1
0.14.0
0.13.9
0.13.8
0.13.7
0.13.6
0.13.5
0.13.4
retired
0.13.3
0.13.2
0.13.0
0.12.1
0.12.0
0.11.1
0.11.0
0.10.1
0.10.0
0.9.4
0.9.3
0.9.2
0.9.1
0.9.0
0.8.2
0.8.1
0.8.0
0.7.0
0.6.1
0.6.0
0.5.2
0.5.1
0.5.0
0.4.2
0.4.1
Nerves System BR - Buildroot based build platform for Nerves Systems
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patches/buildroot/0010-riscv-add-support-for-vector-instructions.patch
From 78538a953e00ec2dda5ca38f578cdc20688e2676 Mon Sep 17 00:00:00 2001
From: Frank Hunleth <fhunleth@troodon-software.com>
Date: Sat, 25 Jun 2022 12:37:27 -0400
Subject: [PATCH] riscv: add support for vector instructions
---
arch/Config.in.riscv | 7 +++++++
arch/arch.mk.riscv | 3 +++
2 files changed, 10 insertions(+)
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index b5e84389e0..2e9576e112 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
config BR2_RISCV_ISA_RVC
bool
+config BR2_RISCV_ISA_RVV
+ bool
+
choice
prompt "Target Architecture Variant"
default BR2_riscv_g
@@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD
config BR2_RISCV_ISA_CUSTOM_RVC
bool "Compressed Instructions (C)"
select BR2_RISCV_ISA_RVC
+
+config BR2_RISCV_ISA_CUSTOM_RVV
+ bool "Vector Instructions (V)"
+ select BR2_RISCV_ISA_RVV
endif
choice
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index 8d2236147c..ee5c434b97 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -26,6 +26,9 @@ endif
ifeq ($(BR2_RISCV_ISA_RVC),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
endif
+ifeq ($(BR2_RISCV_ISA_RVV),y)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
+endif
# Starting from gcc 12.x, csr and fence instructions have been
# separated from the base I instruction set, and special -march
--
2.34.1