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Logical Circuit Simulator using GenServers and Message Passing

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logic_sim lib logic_sim node not.ex
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lib/logic_sim/node/not.ex

defmodule LogicSim.Node.Not do
@moduledoc """
Simple `not` logic gate. One input and one output. Output is opposite of input.
"""
use LogicSim.Node, inputs: [:a], outputs: [:a]
def calculate_outputs(_state, %{a: a} = _input_values) do
%{a: !a}
end
end