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Logical Circuit Simulator using GenServers and Message Passing

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logic_sim lib logic_sim node and.ex
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lib/logic_sim/node/and.ex

defmodule LogicSim.Node.And do
@moduledoc """
Simple `and` logic gate. Two inputs, output is true if both inputs are true, false otherwise.
"""
use LogicSim.Node, inputs: [:a, :b], outputs: [:a]
def calculate_outputs(_state, %{a: a, b: b} = _input_values) do
%{a: a and b}
end
end